[LLVMdev] MachineOperand SubReg

[dag at cray.com]

Jakob Stoklund Olesen <stoklund at 2pi.dk> writes:

>> Aha!  So for physregs, getSubReg() will simply be the exact physical
>> register defined.  Cool, that'll work.
>
> Yes, s/SubReg/Reg/

Right.  :)

>>> Yep, there is no such thing as a 'most super' register. The register
>>> aliasing graph is not a tree. The graph of sub/super-register
>>> relationships is also not a tree, it is a DAG.
>> 
>> Hmm.  I don't doubt it but can you give me an example of a case where
>> there is no "most super" register?  I'm having a hard time thinking up
>> how one would design such an ISA.
>
> The ARM NEON D-registers are 64 bits each. NEON has vld1 instructions that can load 2, 3, or 4 consecutive D-registers.
>
> Two consecutive D-registers is represented by the D0_D1, D1_D2, D2_D3,
> ... super-registers. As you can see, D1 has two super-registers,
> neither is more super than the other.

Wow, that's...interesting.  :)

> This register structure also means that the complete set of aliasing
> registers can get quite large. Some NEON registers have more than 40
> aliases. The register units help control that complexity. Each physreg
> has an associated set of regunits, and two physregs alias if and only
> if their regunit sets overlap. See TRI::regsOverlap().

This must all be post-3.1 stuff since I don't see that here.  Not that
I need it for x86.

Thanks for the helpful explanation!

                             -David