[LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?

[Jakob Stoklund Olesen]

On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote:

> Hi,
> 
> Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations.
> 
> Instructions are defined as follow in TableGen:
>    defm ADD64  : ALU32<"add", 1, 1, addc>;
>    defm ADD64C : ALU32<"addrc", 1, 2, adde>;
> 
> 
> Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly.
> Is there a default guarantee that nothing will ever be inserted between "add" and "addrc" or is there a flag/condition to set somewhere to have that guarantee?

The register allocator expects to be able to insert spill code and copies between any instructions, except terminators.

The only way around that is to use pseudo-instructions that are expanded after RA.

/jakob