[LLVMdev] TableGen list merging

[Jakob Stoklund Olesen]

On Apr 12, 2013, at 10:02 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>> For readability, just combine them explicitly.
> 
> Okay, will do.

Thanks.

>> You may also want to look at ARM's use of optional defs for
>> instructions that can optionally set the flags.
> 
> As far as I can tell, this makes it the job of the C++ code to add the implicit register definition (as is done at the end of ARMBaseInstrInfo::optimizeCompareInstr). Is that right?

Yes, there is also some magic in ARMTargetLowering::AdjustInstrPostInstrSelection() which gets called right after the MI is created.

But it seems like we're still defining ADDS, SUBS, … pseudo-instructions for use by SelectionDAG, so there aren't really any benefits if you're looking for simpler instruction set definitions.

/jakob