[LLVMdev] TableGen list merging

[Hal Finkel]

Hi,

In the PPC backend, there is a "helper" class used to define instructions that implicitly define a condition register:

class isDOT   {
  list<Register> Defs = [CR0];
  bit RC  = 1;
}

and this gets used on instructions such as:

def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
                     "addic. $rD, $rA, $imm", IntGeneral,
                     []>, isDOT;

but there is a small problem. If these instructions are also part of a larger block which also defines registers, like this:

let Defs = [CARRY] in
def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
                     "addic. $rD, $rA, $imm", IntGeneral,
                     []>, isDOT;

then the fact that isDOT puts CR0 into Defs is lost (only CARRY ends up in the list of implicitly-defined registers). How can I modify things to make them work correctly?

Thanks again,
Hal

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory