[LLVMdev] [PATCH] RegScavenger::scavengeRegister

[Hal Finkel]

----- Original Message -----
> From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, "Akira Hatanaka" <ahatanak at gmail.com>
> Sent: Saturday, April 6, 2013 11:56:28 AM
> Subject: Re: [LLVMdev] [PATCH] RegScavenger::scavengeRegister
> 
> 
> On Apr 6, 2013, at 12:42 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> 
> > ----- Original Message -----
> >> From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk>
> >> To: "Akira Hatanaka" <ahatanak at gmail.com>
> >> Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, "Hal
> >> Finkel" <hfinkel at anl.gov>
> >> Sent: Tuesday, March 26, 2013 12:40:44 PM
> >> Subject: Re: [LLVMdev] [PATCH] RegScavenger::scavengeRegister
> >> 
> >> 
> >> On Mar 26, 2013, at 10:29 AM, Akira Hatanaka <ahatanak at gmail.com>
> >> wrote:
> >> 
> >>> The size of general purpose integer registers for mips32 is
> >>> 32-bit
> >>> and accumulators are 64-bit registers consisting of 32-bit hi/lo
> >>> register pairs. So you will need two instructions to copy two
> >>> 32-bit GPR registers to a 64-bit accumulator register. If
> >>> spilling
> >>> to multiple registers is unsupported, perhaps I can I define a
> >>> new
> >>> register class consisting of paired GPR registers and pseudo copy
> >>> instructions?
> >> 
> >> Yes, that would work. Look at the ARM GPRPair register class.
> > 
> > In the PPC case, for CR spilling, the CRs are only really 4 bits;
> > I'd need to define 8-tuples just to pair with 32-bit GPR
> > registers. Under normal circumstances, i32 is the smallest legal
> > type. Instead, to make this work, would I define a 4-bit
> > subregister of the GPRs to hold the data (or maybe 8 bits, and
> > then also use some CR-pair register class)?
> 
> No, that shouldn't be necessary.
> 
> The types on register classes are only used by isel, and this
> register class wouldn't be used before register allocation. Just
> make it [i32], or even [untyped]. (The type is used to pick a
> default spill size, so you may need to 'let Size = 4' if you go with
> untyped).
> 
> Your implementation in copyPhysReg is the final word on what it means
> to copy between registers in this class.
> 
> The register class will not be used automatically without permission
> from your implementation of getLargestLegalSuperClass. This function
> should not allow normal GPR registers to be inflated to the GPR+CR
> super-class because not all registers in that class have enough
> bits.
> 
> X86RegisterInfo::getLargestLegalSuperClass() does something similar
> with the GR8_NOREX register class to work around some awkward x86
> encoding issues with the 20 8-bit registers.

Okay, thanks! So when the RA decides to use this register inflation mechanism, it decides on both the inflation point and the deflation point at the same time? I'd like to understand this better, can you please provide a pointer to the logic for this?

 -Hal

> 
> /jakob
> 
>