[LLVMdev] Target Instructions

[Jafar J]

Hello,

Considering the following MachineInstruction dumped by some SUnit for MIPS target in PostRA-Scheduling “%A1<def> = ADDiu %ZERO, 30”, and the format for the ADDiu instruction is ADDiu rt, rs, immediate. The encoding for the instruction is 001001 rs rt immediate, with lengths of 6, 5, 5, 16 respectively. My question is how to map the operands with their right register? i.e. %A1 = rt, %ZERO = rs, and immediate = 30. Sorry if I didn’t make myself clear enough.

Thanks,
    Jafar J.
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