[LLVMdev] Proposal: New DAG node type for reciprocal operation

[Jim Grosbach]

Sounds like a reasonable fit for a target-specific DAG combine. I suspect a target specific node wouldn't be necessary and the patterns could be matched directly.

-Jim

On Sep 20, 2012, at 3:26 PM, Weiming Zhao <weimingz at codeaurora.org> wrote:

> Hi,
>  
> In relaxed/fast math mode, if we can convert a/b to a * (1/b), we may get more performance when (1) “b” is loop invariant or (2) arch has faster reciprocal instruction (e.g. recipe/recips on ARM)  or (3) arch has no vector div, but has vector mul and recip.
>  
> So ,with this node type, a div node can be converted to a mul and a recip when desired. Then, each arch can further lower the recip node. Even if the arch has no recip support, allowing other passes to hoist  “1/b” out of loop may still be profitable.
>  
> It this feasible?
>  
> Thanks,
> Weiming
>  
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>  
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