[LLVMdev] liveness assertion problem in llc

[Jakob Stoklund Olesen]

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote:

> I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some related commits later on, and the assertion I get on the latest trunk (r164162) differs from what I got on r161643 (where it was the PHIelimination that failed). From the log, I have the impression that the assertion is raised on a dead instruction during the spill weight calculation. The dead instruction (definition of vreg12 in the log below) is an instruction I add during if-conversion for use in a later pass. Previously, such dead instructions did not cause any problem...
> 
> Any idea what might be going wrong here? I've noticed that there is now something like a flag that needs to be set by code transformations that destroy existing liveness information. Maybe I should set that flag during if-conversion? Apart from that, I have no clue…

Hi Bjorn,

It looks like the linked list of operands for a register has been corrupted. Every (non-null) register operand belongs to a doubly linked list of MachineOperands referencing the same register.

I couldn't say how those lists got corrupted based on your debug dumps. The lists are maintained by code in MachineInstr.cpp and MachineRegisterInfo.cpp.

/jakob