[LLVMdev] how to define extending vector load patterns?

[Tim Northover]

>> (set V2I32Regs:$result, (v2i32 (sextloadvi8 ADDRrr:$address)))
>
>
> Thanks, now it accepts the pattern, but it still does not work.
>
> LLVM ERROR: Cannot select: 0x1b98410: v2i32,ch = load 0x2bc86a0, 0x1b9d460,
> 0x25ceb90<LD2[FIXED_STACK7](align=4), sext from v2i8>[ID=365]

Hmm. That's confusing, it looks like that really should match the
patten being used.

I'd add a "-debug" command-line option to llc and look at why the
match fails. It should print out the stages it goes through relative
to the table in XXXGenDAGISel.inc under the build directory. Hopefully
you'll see your pattern tried at some stage, and the line it failed at
should tell you why it didn't match.

The only guess I have is ADDRrr doing something funny, but the
debugging information should make things clearer.

Tim.