[LLVMdev] Problem with PostRASchedulerList.cpp - advice wanted

[Andrew Trick]

On Oct 17, 2012, at 3:33 PM, "Gurd, Preston" <preston.gurd at intel.com> wrote:

> When you compile the attached file using
>  
>   llc -march=x86 -mcpu=atom sched-bug.ll -o –
>  
> The Post-RA scheduler changes the sequence
>  
> movl %ecx, (%esp)
>      bsfl (%esp),%eax # this came from inline assembly code
>  
> to read
>  
>                bsfl (%esp),%eax # this came from inline assembly code
> movl %ecx, (%esp)
>  
> This is an incorrect schedule, because it seems the scheduler is not aware that the memory load by the bsfl depends on  the memory store by the movl.
>  
> If you are familiar with the Post-RA scheduler works, then I would appreciate any suggestions you might have as to how I could fix this problem, such as by treating inline assembly code as a barrier or by including memory references in scheduling decisions.
>  

Hi Preston,

Someone pointed me to a bug filed for this: http://llvm.org/PR13504.

Maybe you can add a memory clobber as a workaround.

-Andy

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