[LLVMdev] RegisterClass constraints in TableGen

[Fraser Cormack]

Hi,

I've come across a problem while working on an LLVM backend for a new
target architecture.

This architecture has two single-ported register files. Each instruction
can only read one operand from each register file, but can write to either.
 I tried implementing it naïvely in TableGen with two definitions per
instruction, so I had:

def AllRegs : RegisterClass< ... (add interleave (XRegs, YRegs))>;

and in the InstrInfo.td:

def Instr_xy: Instruction(outs AllRegs:$dst), (ins XRegs:$src1,
YRegs:$src2), "...", [(set AllRegs:$dst, (OpNode XRegs:$src1, YRegs:$src2))]

def Instr_yx: Instruction(outs AllRegs:$dst), (ins YRegs:$src1,
XRegs:$src2), "...", [(set AllRegs:$dst, (OpNode YRegs:$src1, XRegs:$src2))]

for each instruction. However, upon failing the first match, it insisted on
swapping the registers between the two classes and sticking with that
instruction.

I also tried using ComplexPatterns, but to no avail. I'm sure this is
entirely possible, but I can't see how it's done.

Thanks,
Fraser
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