[LLVMdev] Predicate registers/condition codes question

[Sebastian Pop]

Hi,

On Tue, May 22, 2012 at 11:35 PM, Sebastian Pop <spop at codeaurora.org> wrote:
> Hi Ivan,
>
> On Tue, May 22, 2012 at 5:09 PM, Ivan Llopard <ivanllopard at gmail.com> wrote:
>> Hi Sebastian,
>>
>> On 22/05/2012 23:25, Sebastian Pop wrote:
>>> So my question is how do we specify that for most of the operations i8
>>> should be promoted to i32 and that only a few logical operations are
>>> legal on i8?
>>
>> I think the combo TargetLowerInfo::isTypeDesirableForOp() and
>> IsDesirableToPromoteOp() may help you here. X86 does something similar.
>
> I just tried these functions, and it seems like they are only
> modifying the behavior of type promotions for a small subset of
> operations (PromoteIntBinOp, PromoteIntShiftOp, PromoteExtend,
> PromoteLoad, SimplifyBinOpWithSameOpcodeHands, visitSRL, visitTRUNCATE
> that matter to the performance of i16 on X86.)
>
> I don't like the "desirable" in the name of these functions: in the
> case of Hexagon it is illegal to use an i8 predicate register for
> anything else than setcc, brcond, and the logical ops: so doing the
> conversion is a matter of correctness, not of desirability.
>
> Should I add a call to IsDesirableToPromoteOp in every other operation
> that is currently missing this check for type promotion, or do we want
> a new hook?

I found it pretty difficult to modify the existing DAG combiner to add the
missing calls to isDesirableToPromoteOp, so I abandoned this path.

I found it easier to work with a new integer type p8 for the 8 bit
predicates, such that I can promote i1 into p8 and avoid the confusion
of integer and predicate registers that I had when using the same i8 type.

Would a patch adding the p8 type be ok to commit to llvm?

Thanks,
Sebastian
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