[LLVMdev] TableGen pattern for negated operand

[Joe Matarazzo]

I've been unable to come up with the TableGen recipe to match a
negated operand. My target asm syntax allows the following transform:

  FNEG  r8, r5
  MUL    r6, r8, r9

to

  MUL  r6, -r5, r9

Is there a Pattern<> syntax that would allow matching *any* opcode (or
even some subset), not just MUL, with a FNEG'd operand? I expect I can
define a PatFrag:

def fneg_su : PatFrag<(ops node:$val), (fneg node:$val), [{ return
N->hasOneUse(); }]>;

and then use that in each target instruction patten in XXXInstrInfo.td, such as:

def XXX_MUL : XXXInst<
   (outs GPR32:$dst),
   (ins GPR32:$src1, GPR32:$src2),
   "mul $dst, -$src1, $src2",
   [(set $dst, (mul (fneg_su GPR32:$src1), GPR32:$src2))]>;

but I would like to believe there's a way to do this with a Pattern<>
definition instead, with help from PatFrag and the SDNode_XFORM
perhaps.

I looked at the ARM target code with PatFrag for negated immediates
but that approach doesn't seem possible with register operands, as I
don't know what xform would operate on. With immediates you have a DAG
node you can generate.

Also, it does seem like this is a folding operation
PerformDAGCombine() could do but that approach seems like it needs to
modify the registerclass, or something similar, that would eventually
get you to a PrintMethod that could insert the dash/negate in front of
the operand. I didn't want to define a 'mirror' registerclass for my
existing register set that would just have the Name as the negated
version. That would have its own complications. Is there a superior
way to do this with DAG combine?

Thanks,
Joe