[LLVMdev] tablegen question

[WANG.Jiong]

>From my understanding, NAME is a special builtin entry and dedicated for
things related multiclass,

So, is the following rewrite what you want?

class Base<int V> {
   int Value = V;
}

class Derived<string Truth> :
   Base<!if(!eq(Truth, "true"), 1, 0)>;

multiclass Derived_m<string T> {
  def #NAME# : Derived<T>;
}

defm TRUE : Derived_m<"true">;
defm FALSE : Derived_m<"false">;

tablegen result:

------------- Classes -----------------
class Base<int Base:V = ?> {
  int Value = Base:V;
  string NAME = ?;
}
class Derived<string Derived:Truth = ?> {    // Base
  int Value = !if(!eq(Derived:Truth, "true"), 1, 0);
  string NAME = ?;
}
------------- Defs -----------------
def FALSE {    // Base Derived !strconcat(NAME, "")
  int Value = 0;
  string NAME = "FALSE";
}
def TRUE {    // Base Derived !strconcat(NAME, "")
  int Value = 1;
  string NAME = "TRUE";
}

---
Regards,
WANG.Jiong

On 03/16/2012 09:55 PM, Reed Kotler wrote:
> Trying to resolve some general tablegen questions.
>
> Consider the test case for Tablegen called eq.td
>
> class Base<int V> {
>    int Value = V;
> }
>
> class Derived<string Truth> :
>    Base<!if(!eq(Truth, "true"), 1, 0)>;
>
> def TRUE : Derived<"true">;
> def FALSE : Derived<"false">;
>
> If I process this through tablegen I get:
>
> ------------- Classes -----------------
> class Base<int Base:V = ?> {
>    int Value = Base:V;
>    string NAME = ?;
> }
> class Derived<string Derived:Truth = ?> {    // Base
>    int Value = !if(!eq(Derived:Truth, "true"), 1, 0);
>    string NAME = ?;
> }
> ------------- Defs -----------------
> def FALSE {    // Base Derived
>    int Value = 0;
>    string NAME = ?;
> }
> def TRUE {    // Base Derived
>    int Value = 1;
>    string NAME = ?;
> }
>
> Why is NAME=? in FALSE and TRUE.
>
> Shouldn't it be FALSE and TRUE ??
>
>
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