[LLVMdev] apparent mistake in several ports register td file ???

[reed kotler]

The field Num seems to have no meaning. It is not recognized by the 
backend tools. It does not hurt anything but should not be there.

// We have banks of 32 registers each.
class MipsReg<string n> : Register<n> {
   field bits<5> Num;
   let Namespace = "Mips";
}

class ARMReg<bits<4> num, string n, list<Register> subregs = []> : 
Register<n> {
   field bits<4> Num;
   let Namespace = "ARM";
   let SubRegs = subregs;
   // All bits of ARM registers with sub-registers are covered by 
sub-registers.
   let CoveredBySubRegs = 1;
}

class ARMFReg<bits<6> num, string n> : Register<n> {
   field bits<6> Num;
   let Namespace = "ARM";
}

class SparcReg<string n> : Register<n> {
   field bits<5> Num;
   let Namespace = "SP";
}




Then subsequently, further derived types copy the mistake.

// Registers are identified with 5-bit ID numbers.
// Ri - 32-bit integer registers
class Ri<bits<5> num, string n> : SparcReg<n> {
   let Num = num;
}
// Rf - 32-bit floating-point registers
class Rf<bits<5> num, string n> : SparcReg<n> {
   let Num = num;
}
// Rd - Slots in the FP register file for 64-bit floating-point values.
class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
   let Num = num;
   let SubRegs = subregs;
   let SubRegIndices = [sub_even, sub_odd];
   let CoveredBySubRegs = 1;
}

......
// Mips CPU Registers
class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
   let Num = num;
}