[LLVMdev] commit r152019 broke architectures with more than 255 registers

[Jakob Stoklund Olesen]

On Mar 5, 2012, at 10:40 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:

> 
> On Mar 5, 2012, at 5:39 AM, Heikki Kultala wrote:
> 
>> Our architecture(TCE) can have LOTS of registers.
>> 
>> It seems r152019 changed some register bookkeeping data structures to 
>> 8-bit. This broke support for architectures with >255 registers.
>> 
>> Please revert this change or make those register-related values at least 
>> 16 bits wide.
> 
> I agree. We can limit the number of physregs to 64k, but no more.

I have reverted the commits that limited the concatenated register and instruction names to 64k. They would have caused problems for a 16k register target.

Heikki, please let me know if you are having problems with the limits enforced by TableGen now.

/jakob