[LLVMdev] Register coalescing

[Joe Matarazzo]

Need some guidance about the right way to model this -- how would you model
a backend with a handful of read-only physical registers that are passed as
arguments to a function? I was emitting copyFromReg nodes in the
LowerFormalArgument() routine, but then the register allocator and
coalescer are resisting coalescing the COPY MI's for various reasons - for
example, the read-only register class contains too few registers and the
live range threshold cancels the coalescing.

A simple example (post-ISEL):

%vreg2<def> = COPY %C1; GPReg:%vreg2
...
%vreg11<def> = MUL %vreg7, %vreg2; GPreg:%vreg11,%vreg7,%vreg2

I'd want it to propagate %C1 into the MUL, replacing %vreg2. How is this
supposed to work? Is there a DAG operation or MF pass that should handle
this before regalloc, or some other means?

Thanks,
Joe
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120308/0f85703b/attachment.html>