[LLVMdev] Predicate registers/condition codes question

[Tony Linthicum]

On 3/1/2012 2:21 PM, Eli Friedman wrote:
> On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum<tlinth at codeaurora.org>  wrote:
>> Hey folks,
>>
>> We are having some difficulty with how we have been representing our
>> predicate registers, and wanted some advice from the list.  First, we
>> had been representing our predicate registers as 1 bit (i1).  The truth,
>> however, is that they are 8 bits.  The reason for this is that they
>> serve as predicates for conditional execution of instructions,  branch
>> condition codes, and also as vector mask registers for conditional
>> selection of vector elements.
>>
>> We have run into problems with type mismatches with intrinsics for some
>> of our vector operations.  We decided to try to solve it by representing
>> the predicate registers as what they really are, namely i8.  We changed
>> our intrinsic and instruction definitions accordingly, changed the data
>> type of the predicate registers to be i8, and changed
>> getSetCCResultType() to return i8.  After doing this, the compiler
>> builds just fine but dies at runtime trying to match some target
>> independent operations (e.g. setcc/brcond) that appear to want an i1 for
>> the condition code.
>>
>> So, my question is this: is it even possible to represent our predicate
>> registers (and our condition codes) as i8, and if so, what hook are we
>> missing?
>
> Making getSetCCResultType return i8 is definitely supported, and
> brcond should be okay with that.  It's not obvious what is going
> wrong; are you sure there isn't anything in your target still
> expecting an i1?
>
> -Eli

Thanks, Eli.  We'll take another look at our target dependent 
information to see if some i1's are still lurking about.  It's good to 
know that this should work.

Tony

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