[LLVMdev] commit r152019 broke architectures with more than 255 registers

[Villmow, Micah]

Ughh... yeah I would have to agree here. The AMDIL backend uses more than 256 registers to model its register file correctly.

> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Heikki Kultala
> Sent: Monday, March 05, 2012 5:39 AM
> To: LLVM Dev
> Subject: [LLVMdev] commit r152019 broke architectures with more than
> 255 registers
> 
> Our architecture(TCE) can have LOTS of registers.
> 
> It seems r152019 changed some register bookkeeping data structures to
> 8-bit. This broke support for architectures with >255 registers.
> 
> Please revert this change or make those register-related values at
> least
> 16 bits wide.
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