[LLVMdev] RE : Is llc broken for Cortex-A9 + neon ?

[Sebastien DELDON-GNB]

Hi Anton & Nadav,

I filled this problem a while ago here http://llvm.org/bugs/show_bug.cgi?id=13111
Thinking it first was an LLVM opt bug. Shall I assign it to Nadav or create a new one ?

Seb
________________________________________
De : Anton Korobeynikov [anton at korobeynikov.info]
Date d'envoi : lundi 25 juin 2012 15:31
À : Sebastien DELDON-GNB
Cc : LLVMdev at cs.uiuc.edu; Rotem, Nadav
Objet : Re: [LLVMdev] Is llc broken for Cortex-A9 + neon ?

Sounds like a bug in vector promote. If I restore this flag and use
-promote-elements=0 everything works for me.

Please fill a PR in LLVM bugzilla and assign to Nadav.

On Mon, Jun 25, 2012 at 5:04 PM, Sebastien DELDON-GNB
<sebastien.deldon at st.com> wrote:
> Hi all,
>
>
> considering following .ll file
>
> ; ModuleID = 'vect3x.ll'
> target triple = "armv7-none-linux-gnueabi"
>
> define arm_aapcscc void @test_hi_char8(i8* %.T0351, <8 x i8>* nocapture %srcA, <4 x i8>* nocapture %dst) noinline {
> L.entry:
>  %0 = tail call arm_aapcscc  i32 (...)* @get_global_id(i8* %.T0351, i32 0)
>  %1 = bitcast <8 x i8>* %srcA to <4 x i8>*
>  %2 = getelementptr <4 x i8>* %1, i32 0, i32 4
>  %3 = bitcast i8* %2 to <4 x i8>*
>  %4 = shl i32 %0, 3
>  %5 = getelementptr <4 x i8>* %3, i32 0, i32 %4
>  %6 = bitcast i8* %5 to <4 x i8>*
>  %7 = load <4 x i8>* %6, align 1
>  %8 = shl i32 %0, 2
>  %9 = getelementptr <4 x i8>* %dst, i32 0, i32 %8
>  %10 = bitcast i8* %9 to <4 x i8>*
>  store <4 x i8> %7, <4 x i8>* %10, align 4
>  ret void
> }
>
> declare arm_aapcscc i32 @get_global_id(...) readonly
>
> When use llc 3.0 on it as follows: llc vect3x.ll -march=arm -mcpu=cortex-a9 -relocation-model=pic -o vect3x.s it compiles.
> When I use llc trunk or llc 3.1 it fails on an assert:
> llc: /work1/tools/llvm/trunk/sources/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:703: void<unnamed>::SelectionDAGLegalize::LegalizeOp(llvm::SDNode*): Assertion `TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) == TargetLowering::TypeLegal && "Unexpected illegal type!"' failed.
> 0  libLLVM-3.2svn.so 0x00007fe073e4433f
> 1  libLLVM-3.2svn.so 0x00007fe073e4654a
> 2  libpthread.so.0   0x00007fe072d9d8f0
> 3  libc.so.6         0x00007fe07208ca75 gsignal + 53
> 4  libc.so.6         0x00007fe0720905c0 abort + 384
> 5  libc.so.6         0x00007fe072085941 __assert_fail + 241
> 6  libLLVM-3.2svn.so 0x00007fe073cba4da
> 7  libLLVM-3.2svn.so 0x00007fe073cbcccd llvm::SelectionDAG::Legalize() + 269
> 8  libLLVM-3.2svn.so 0x00007fe073dc4e84 llvm::SelectionDAGISel::CodeGenAndEmitDAG() + 1076
> 9  libLLVM-3.2svn.so 0x00007fe073dc7551 llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::Instruction const>, llvm::ilist_iterator<llvm::Instruction const>, bool&) + 273
> 10 libLLVM-3.2svn.so 0x00007fe073dc7f17 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) + 2439
> 11 libLLVM-3.2svn.so 0x00007fe073dc902b llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 1147
> 12 libLLVM-3.2svn.so 0x00007fe07386a98d llvm::FPPassManager::runOnFunction(llvm::Function&) + 557
> 13 libLLVM-3.2svn.so 0x00007fe07386aa73 llvm::FPPassManager::runOnModule(llvm::Module&) + 51
> 14 libLLVM-3.2svn.so 0x00007fe07386a501 llvm::MPPassManager::runOnModule(llvm::Module&) + 497
> 15 libLLVM-3.2svn.so 0x00007fe07386a67b llvm::PassManagerImpl::run(llvm::Module&) + 171
> 16 llc               0x000000000040a302 main + 4642
> 17 libc.so.6         0x00007fe072077c4d __libc_start_main + 253
> 18 llc               0x0000000000406149
> Stack dump:
> 0.      Program arguments: /work1/tools/llvm/trunk/install/bin/llc vect3x.ll -march=arm -mcpu=cortex-a9 -relocation-model=pic -print-before-all -o vext3x.s
> 1.      Running pass 'Function Pass Manager' on module 'vect3x.ll'.
> 2.      Running pass 'ARM Instruction Selection' on function '@test_hi_char8'
> Abort
>
>
> Is there something wrong in .ll file ? Same file is compiled by llc with -mattr=-neon disabling NEON) or when targeting x86.
> What this assert means ?
> Thanks for your answer.
> Best Regards
> Seb
>
>
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--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University