[LLVMdev] Boolean floats and v4i1

[Hal Finkel]

Hello,

I'm working on support for the SIMD instruction set on our new BG/Q
supercomputer. This instruction set is v4f64 (with the exception of
some int <-> fp conversions, floating-point only). The vectorized
comparisons, logical operations and selects also exclusively use
floating-point inputs. For those inputs that are logically vectors of
booleans the system uses the following convention: positive numbers are
true, everything else (including NaNs) are false. The outputs of
logical operations are -1.0 and 1.0.

I am not sure how to best support this in LLVM. LLVM does not have
an MVT::v4i1. One thing that I can do (without modifying LLVM core) is
to add v4i64 to the vector registers, and pretend that the v4i1 is being
promoted to that type (I match loads and stores to pairs of memory
operations and fp<->int conversions). This works somewhat (CodeGen will
happily generate vectorized selects, comparisons and logical ops on the
comparison results), but leaves me with a broken v4i64 type (it is
broken because the operations defined on that type only essentially
respect the sign bit of the numbers -- so long as these are used only
for the promoted v4i1 operations almost everything is fine, but these
operations are not true v4i64 operations).

What should I do here? Should I add MVT::v?i1 types so that they can be
directly used without promotion?

Thanks again,
Hal

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory