[LLVMdev] Post-RA Def/Use Information

[Owen Anderson]

On Jun 15, 2012, at 3:07 PM, Joshua Cranmer <pidgeot18 at gmail.com> wrote:

> On 6/15/2012 6:00 PM, Owen Anderson wrote:
>> On Jun 15, 2012, at 2:54 PM, dag at cray.com wrote:
>> 
>>> Looking through TOT sources, I don't see anything that would provide
>>> def/use chains (or equivalent information) post register allocation.  I
>>> would like to write some peeps to clean up various target-specific
>>> things but for safety I will need such information.
>>> 
>>> Is such an analysis pass available somewhere that I've missed?  If not,
>>> is there a better way to find all uses of a defined value post register
>>> allocation?  Writing a def/use chain pass would not be hard but if the
>>> information is already there I'd rather avoid that cost.  :)
>> Do the MachineRegisterInfo::def_begin/def_end/use_begin/use_end iterators not work on physical registers?
>> 
> 
> I seem to recall, the last time I used those, that they ended up being a 
> fairly flat list of all definitions and all uses of a physical 
> registers, not all the uses of a particular definition (or vice versa).


Right, the code is no longer in SSA form at this point.  If we want to get SSA information at this level, I suspect you want to be querying LiveIntervals, which has that information, assuming it's still live.

--Owen