[LLVMdev] non-SSA IR generation

[amruth.rd at knights.ucf.edu]

Hi Jiesheng,
I did try that. Below is the command I used to generate the bit code file using clang.
clang -emit-llvm sample.cpp -S -o sample.ll
I am not sure if I need to take out -emit-llvm option too.The resulting bit code file had instances with variables being assigned only once though it did not contain any phi nodes. My understanding is that code could be in SSA form even without having phi nodes.  I am not running any opt modules on the code.  
Please correct me if I am wrong. 
Cheers,Amruth 
From: jwei at ece.ubc.ca
Date: Wed, 13 Jun 2012 14:00:17 -0700
Subject: Re: [LLVMdev] non-SSA IR generation
To: amruth.rd at knights.ucf.edu
CC: llvmdev at cs.uiuc.edu

Hi Amruth,
If you do not specify any optimization flag for 'clang' and do not run 'opt -mem2reg' pass on the generated IR file, it is in non-SSA form. However, many variables stay in memory instead of registers in this case.


Thanks,Jiesheng

On Wed, Jun 13, 2012 at 1:17 PM,  <amruth.rd at knights.ucf.edu> wrote:






I am experimenting with LLVM optimizer and found that the bit code file clang emits is already in SSA form, but I want to generate it in non-SSA form. Would you let me know if there is any way of doing it? 


Cheera,Amruth 		 	   		  

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