[LLVMdev] scoreboard hazard det. and instruction groupings

[Andrew Trick]

On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Looking at VLIWPacketizerList::PacketizeMIs, it seems like the

> instructions are first scheduled (via some external scheme?), and then
> packetized 'in order'. Is that correct?

Anshu?

> In the PowerPC grouping scheme, resources are assigned on a group
> basis (by the instruction dispatching stages). However, once the group
> is dispatched to the appropriate functional units, 'bypass' is still
> available on an instruction-by-instruction basis to instructions in
> later groups. Final writeback waits until all members of the group
> complete.
> 
>> 
>> Ideally, you can express your constraints using InstrStage itinerary
>> entries. 
> 
> I don't see how, in the current scheme, to express that an instruction
> must wait in FU0 until there are also waiting instructions in FU1, FU2
> and FU3. Furthermore, there are certain constraints on what those
> instructions can be, and which ones will move forward as the next
> dispatched group, and I think we need to fallback into C++ to deal with
> them.

Right. I should have mentioned that the static itinerary really can't express dynamic constraints. You can play games by inventing new types of FuncUnits. But there's no way to say an instruction hogs a pipeline until some future event at unknown interval.

-Andy