[LLVMdev] scoreboard hazard det. and instruction groupings

[Hal Finkel]

I'm considering writing more-detailed itineraries for some PowerPC CPUs
that use the 'traditional' instruction grouping scheme. In essence,
this means that multiple instructions will stall in some pipeline stage
until a complete group is formed, then all will continue.

I expect to provide CPU-specific code to help determine when the
currently-waiting instructions would form a group. Is there a
straightforward way that I could override the scoreboard hazard
detector (or layer on top of it) to insert this kind of logic?

Should I instead be looking to do something like what Hexagon does
for VLIW cores? I think the main difference between the PowerPC scheme
and a VLIW scheme, is that the CPU itself can form groups internally,
it is just more efficient if the groups are provided pre-made. Maybe
this difference, if it is one, is insignificant.

Thanks again,
Hal

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory