[LLVMdev] Predicate registers/condition codes question

[Sebastian Pop]

On Sun, Jun 3, 2012 at 7:11 AM, Ivan Llopard <ivanllopard at gmail.com> wrote:
>> So the solution that I was investigating looks like this:
>>
>>      for (unsigned int i = 0; i<  ISD::BUILTIN_OP_END; ++i) {
>>        switch (i) {
>>        // By default all operations on i8 have to be promoted to i32.
>>        default:
>>          setOperationAction(i, MVT::i8, Custom);
>>          break;
>>
>>        // Only the following operations are legal on i8 predicates.
>>        case ISD::AND:
>>        case ISD::OR:
>>        case ISD::XOR:
>>        case ISD::SETCC:
>>        case ISD::SIGN_EXTEND:
>>         break;
>>        }
>>      }
>>
>> and promote all i8 to i32 in HexagonTargetLowering::LowerOperation
>
> That's hard work!

Indeed, that was my concern as well: that's why I tried to avoid using
i8 for predicates and use p8, but now I know that is a dead-end.

> Why don't you call it with "Promote" instead of
> "Custom" and let the Legalizer do the job? Does it not work?

I tried this, and the legalizer will happily say that i8 is a legal type
and just return the exact same node: this is because we declared
that Hexagon has a register for i8, that makes i8 legal for all
promotions.

Sebastian
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