[LLVMdev] X86 sub_ss and sub_sd sub-register indexes

[dag at cray.com]

Jakob Stoklund Olesen <jolesen at apple.com> writes:

>> What happens if the result of the above pattern using COPY_TO_REGCLASS
>> is spilled?  Will we get a 64-bit store or a 128-bit store?
>
> This behavior isn't affected by the change. FR64 registers are spilled
> with 64-bit stores, and VR128 registers are spilled with 128-bit
> stores.
>
> When the register coalescer removes a copy between VR128 and FR64
> registers, it chooses the larger spill size for the result. This is
> the same for sub-register copies and full register copies.

So if I understand this correctly, a pattern like this:

  def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
            (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;

will currently use a 128-bit store if it is spilled?

That's really not good.

If the 128-bit register is not ever used as a 128-bit register,
shouldn't the coalescer pick the 64- or 32-bit register?

                                   -Dave