[LLVMdev] Question about an unusual jump instruction

[Jakob Stoklund Olesen]

On Jul 25, 2012, at 1:55 AM, Michele Scandale <michele.scandale at gmail.com> wrote:
> 
> I took a quick look to PPCCTRLoops.cpp, but I don't think it's the same of my 
> case. The instruction I have defines explicitly a GPR register, while the BDNZ 
> defines and uses an implicit dedicated register. I based my optimization pass on 
> what seen in Hexagon target too, but due to the fact that I have an explicit GPR 
> as loop counter, my instruction defines a virtual register and the fact that the 
> instruction is also a terminator creates all the problems I listed in my 
> previous mail.

Hi Michele,

As you've already figured out on your own, LLVM's register allocator passes don't support terminators that write virtual registers.

You could try forming your DECJNZ instructions after register allocation.

/jakob