[LLVMdev] Help with PPC64 JIT

Adhemerval Zanella azanella at linux.vnet.ibm.com
Thu Jul 19 12:50:49 PDT 2012


Hello,

I am currently working with PPC64 JIT support for LLVM. So far I could make function calls
work by adding function descriptors in 'lib/Target/PowerPC/PPCJITInfo.h' and adding a
virtual method at 'LLVM::TargetJITInfo' that is called within 'JITEmitter::finishFunction'
just after 'sys::Memory::InvalidateInstructionCache' to update the Global Mapping with
function descriptor instead of the function address. The JIT function descriptor is 
loaded correctly in 'JIT::runFunction', instead of assuming the JIT function code is
an ODP.

Now I'm trying to make the relocation work properly. Using the testcase '2003-01-04-ArgumentBug'
the assembly generated for main functions is the following: 

.L.main:
# BB#0:
        mflr 0
        std 0, 16(1)
        stdu 1, -112(1)
        lis 3, .LCPI1_0 at ha
        li 4, 1
        lfs 1, .LCPI1_0 at l(3)
        li 3, 0
        bl foo 
        nop 
        addi 1, 1, 112 
        ld 0, 16(1)
        mtlr 0
        blr 

Which is correct, however for the JIT one generated in memory the relocations generate some issues.

First the 'lis 3, .LCPI1_0 at ha' can possible overflow which will generate an wrong relocation.
Since the const data will be place just before the function code in JIT generation, my first
approach was to point the functions descriptor TOC to the JIT function base, so the 'lis' relocation
could be rewritten as 'addis 3,2,.LCPI1 at TOC@ha'.

And there where I could use some help: is it the best approach? Where is the best place to make this
kind of analysis? Is there another way to make code adjustments for JIT?

At fist I though to put the logic at 'lib/Target/PowerPC/PPCJITInfo.cpp', but from what I could
understand the 'relocate' function method is indeed just to operate on the relocation
addresses, not to change the upcode.

Any advices/tips/suggestion would be appreciated.

-- 
Adhemerval Zanella Netto
  Software Engineer
  Linux Technology Center Brazil
  Toolchain / GLIBC on Power Architecture
  azanella at linux.vnet.ibm.com / azanella at br.ibm.com
  +55 61 8642-9890




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