[LLVMdev] Tile64 bundle-types and VLIW infrastructure

[Juhasz David]

Hello,

I've made a backend for Tile64 processor as my master's thesis. Of 
course, there is a lot to do in order to harness all the power of the
processor, but LLVM programs already can be compiled to tile assembly.
If anyone interested in the backend, just let me know and I release the
code on our project site.

One way to improve my backend is to utilize its ILP capabilities, so
I'd really like to use the new VLIW infrastructure of LLVM 3.1. My 
problem is the following:

The processor consists of three parallel pipelines, however there are
two types of bundles: two-wide (X) and three-wide (Y) bundles. All of
the instructions can packed into X-bundles, but using Y-bundles would
be more efficient. Too bad, Y-bundles can't contain arbitrary
instructions.

So, there are 5 virtual pipelines: X0, X1, Y0, Y1, Y2. I can define
that which pipelines can be used to perform an instruction. On the
other hand, AFAIK one subtarget can be matched only with one
ProcessorItineraries and all its FuncUnits may be used in each bundle.
Thus, I can't constraint bundles to use either X0, X1 or Y0, Y1, Y2, and
never mix them.

Is there a way to define two types of bundles using the current
capabilities of TableGen and CodeGen? Or had I better use only X-bundles
for now?

Thanks for any suggestions,
David