[LLVMdev] Issue with Machine Verifier and earlyclobber

[Borja Ferrer]

Hello,

I'm getting a machine verifier error after introducing the earlyclobber
constraint to some instructions where the src and dest regs can't be the
same. The offending instruction pattern is this one:

let canFoldAsLoad = 1,
isReMaterializable = 1,
Constraints = "@earlyclobber $dst" in
def LDDWRdPtrQ : Inst<(outs DREGS:$dst),
                        (ins memri:$src),
                        "lddw\t$dst, $src",
                        [(set DREGS:$dst, (load addr:$src))]>;

This is just a load with displacement instruction of the form "load reg,
[reg_addr+<offs>]", where reg_addr and dest can't be the same register.

This caused the following verifier error:

*** Bad machine code: No live range at def ***
- function:    f3
- basic block: entry 0x9d68664 (BB#0) [0B;5056B)
- instruction: 3688B    %vreg96<earlyclobber,def> = LDDWRdPtrQ <fi#0>, 0;
mem:LD2[FixedStack0](align=1) DREGS:%vreg96
- operand 0:   %vreg96<earlyclobber,def>
3688e is not live in [3688r,4480r:0)  0 at 3688r

*** Bad machine code: Early clobber def must be at an early-clobber slot ***
- function:    f3
Valno #0 is defined at 3688r in [3688r,4480r:0)  0 at 3688r

I've noticed this only happens when loading from frame indexes like in this
case, regular loads won't error.

Does anybody know what is causing this sort of error or if I'm missing
something obvious? I can provide any other debug info if requested.

Thanks in advance.
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