[LLVMdev] How to specify that Src Reg and Dest Reg can't be the same in td?

[陳韋任 (Wei-Ren Chen)]

Hi Ivan,

> I don't think you can model it with Constraints in td files. You may try 
> to put a regalloc hint in src and dst operands of the instructions you 
> are interested.
> See getRawAllocationOrder(), ResolveRegAllocHint() and 
> UpdateRegAllocHint() hooks in TargetRegisterInfo. ARM has good examples 
> on how to implements them.

  Thanks for your reply!

  I found @earlyclobber can be used in td to achieve my goal. 
Here is the thread talked about @earlyclobber,
  http://llvm.1065342.n5.nabble.com/Early-clobber-constraint-in-TableGen-td41599.html

Regards,
chenwj

-- 
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj