[LLVMdev] question on table gen TIED_TO constraint

[Evan Cheng]

On Jul 9, 2012, at 4:15 PM, Manman Ren <mren at apple.com> wrote:

> 
> I need to implement an instruction which has 2 read-write registers, so I added
> let Constraints = "$src1 = $dst, $mask = $mask_wb" in {
> ...
>  def rm  : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
>            (ins VR128:$src1, v128mem:$src2, VR128:$mask),
> ...
> }
> There is a problem since MRMSrcMem assumes the 2nd physical operand is a memory operand.
> See the section about MRMSrcMem in RecognizableInstr::emitInstructionSpecifier.

Can this be fixed?

Evan

> And the above gives us $dst, $mask_wb, $src1, $mem, $mask, and $mask_wb is the second physical operand.
> 
> I thought about using "$mask_wb = $mask", but it breaks the assumption of TIED_TO LhsIdx > RhsIdx.
> Is adding another addressing mode a good idea?
> 
> Any pointer is appreciated.
> Thanks,
> Manman
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