[LLVMdev] bug in tablegen?

[reed kotler]

I've filed the following bug. Maybe I'm doing something stupid here or 
maybe someone knows of a workaround.

The following fragment from mips16 (not yet checked into main source).

The problem is that I should be able to pass parameters:
I.OutOperandList, I.InOperandList

But instead, I must back substitute what I know the values of these are.
(outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz)


class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, 
InstrItinClass itin> :
         FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, 
CPU16Regs:$ry),
                   !strconcat(asmstr, "\t$rz, $rx, $ry"),
                    pattern, itin>;

class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>:
   FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz),
               // tablegen bug: should be I.OutOperandList, I.InOperandList,
      I.AsmString,
      [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], 
I.Itinerary > {
   let isCommutable = isComm;
   let isReMaterializable = 1;
}