[LLVMdev] Problem generating <target>GenAsmMatcher.inc

[Carter, Jack]

I believe that table gen builds MipsGenAsmMatcher.inc which has the Match routines like MatchRegisterName().

In building MipsGenAsmMatcher.inc I am hitting the following issue (actually several, but they may be related). It may have something to do with the $$ escape sequence:

/home/jcarter/workarea/llvm/lib/Target/Mips/Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero'
def DSDIV    : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;

Here is the sequence of definitions:

def SDT_MipsDivRem       : SDTypeProfile<0, 2,
                                         [SDTCisInt<0>,
                                          SDTCisSameAs<0, 1>]>;

def MipsDivRem    : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
                           [SDNPOutGlue]>;

class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
          RegisterClass RC, list<Register> DefRegs>:
  FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
     !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
     [(op RC:$rs, RC:$rt)], itin> {
  let rd = 0;
  let shamt = 0;
  let Defs = DefRegs;
}


Note:,there doesn't seem to be an issue with the 32 bit versions which seem to be the following the same pattern. Also, the 64 bit version is in its' own td, though I don't know why that would matter.

class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
  Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;

def SDIV    : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
def UDIV    : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;

Jack
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