[LLVMdev] CodeGen instructions and patterns
Jim Grosbach
grosbach at apple.com
Fri Feb 24 12:35:42 PST 2012
(readding cc llvmdev)
On Feb 24, 2012, at 11:46 AM, محمد ﻋﻤﺮ ﺩﻫﻠﻮﻯ <omerbeg at gmail.com> wrote:
>
> > otherwise how are the machine instructions being accessed/matched for instruction selection ?
> >
>
> Have a look at the code in SelectionDAGISel.
>
>
> I am looking at the ARM backend.
> In specific, the instruction selection.
> In Select(N), I only see ad-hoc matches on the basis of the opcode in the provided SDNode of the DAG, and then getMachineNode() is being used to generate the machine instruction.
> Am I understanding this correctly ?
>
That's just the target-specific part. Also look in lib/CodeGen/SelectionDAG.
You may find the debug output from the compiler useful. Try running llc with the "-debug-only=isel" command line option. That will give lots of information about how the selector is going about figuring out which patterns to use.
-Jim
> Consider the following multiply add insstruction, given in ARMInstrInfo.td
>
> def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
> IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
> [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>
>
> How do I get this instruction and it corresponding pattern in the selector ?
>
> -Omer
>
>
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120224/ab5c00a6/attachment.html>
More information about the llvm-dev
mailing list