[LLVMdev] Query Regarding instruction ordering of passive nodes

[KARTHIKVENKATESH BHAT]

Hi All,
I'm trying to compile the attached code(gdb11531.c) with latest clang with -O0 on ARM. 
Clang seems to be reordering the instructions in case of constant nodes(for ARM) even when O0 is specified resulting in few wrong information when debugging through GDB. 
I had few queries,would be great if someone could clarify the same -

In the given assembly code, the instructions where constant data is copied into registers are marked with wrong location information.

Eg:

mov       r0, #5
mov       r1, #56
are marked with line number 34 where as in source assembly, myrec.z = 56; is at line number 36.

mov       r0, #78
is marked at line number 36 where as in source assembly, myrec.x = 78; is at line number 37.

It is observed that such nodes are not updated with correction debug location info, hence they are generally placed at the top of the finally generated assembly code. Is this by design intentionally? 
If so, why ? 

Tried updating the debugloc info for constant sdnodes as per http://llvm.org/bugs/show_bug.cgi?id=13269 by just modifying for getConstant APIs
It results in duplicate debug location info for same line numbers as attached in gdb11531_getConstant_modified.s

In addition, passive nodes are omitted from scheduled during instruction scheduling such that they are free to be placed anywhere while generating the instruction sequence. Is this related with above problem of debug location ?

The list of passive nodes are :-

ConstantSDNode
ConstantFPSDNode
RegisterSDNode
RegisterMaskSDNode
GlobalAddressSDNode
BasicBlockSDNode
FrameIndexSDNode
ConstantPoolSDNode
JumpTableSDNode
ExternalSymbolSDNode
BlockAddressSDNode
MDNodeSDNode

Thanks
Karthik



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