[LLVMdev] Increase the number of registers in ARM

[David Chisnall]

On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:

>  The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> should look into,
> 
> // Integer registers
> def R0  : ARMReg< 0, "r0">,  DwarfRegNum<[0]>;
> def R1  : ARMReg< 1, "r1">,  DwarfRegNum<[1]>;
> 
>  ...

That's the easy part.  ARM (AArch32) has 16 registers because register operands are stored in a 4-bit bitfield in the instructions.  If you want to add more registers, then you will also need to modify the instruction encoding of every instruction, or place them in a separate namespace (as with the NEON / VFP registers) and add instructions for explicitly modifying them.

David