[LLVMdev] PHI

[Jakob Stoklund Olesen]

That PHI instruction has completely wrong operands, and the other verifier error also suggests something is very wrong.

No pass should create a PHI like that.

/jakob

On Aug 29, 2012, at 8:45 PM, reed kotler <rkotler at mips.com> wrote:

> I'm getting this error in my mips16 port. I think that PHI replacement is done in some target independent phase. In the process of debugging this. Maybe to someone else it's obvious how this can happen .
> 
> tia,
> Reed
> 
> *** Bad machine code: MBB exits via unconditional fall-through but its successor differs from its CFG successor! ***
> - function:    main
> - basic block: BB#0 entry (0x2412320)
> 
> *** Bad machine code: PHI operand is not in the CFG ***
> - function:    main
> - basic block: BB#0 entry (0x2412320)
> - instruction: PHI <BB#1>
> - operand 0: <BB#1>
> LLVM ERROR: Found 2 machine code errors.
> 
> ....
> 
> From trace:
> 
> 0.    Program arguments: /home/rkotler/llvmpb/install/bin/llc -mcpu=mips16 forloop1.ll -march=mipsel -relocation-model=pic -o forloop1.s -O3
> 1.    Running pass 'Function Pass Manager' on module 'forloop1.ll'.
> 2.    Running pass 'Mips Assembly Printer' on function '@main'
> Aborted
> rkotler at ubuntu-rkotler:~/workspace/llvm_base_test/src$ /home/rkotler/llvmpb/install/bin/llc -mcpu=mips16 forloop1.ll -march=mipsel -relocation-model=pic -o forloop1.s -O3  -verify-machineinstrs   -verify-loop-info  -verify-dom-info -verify-regalloc
> 
> # After machine block placement.
> # Machine code for function main: Post SSA
> Frame Objects:
>  fi#0: size=4, align=4, at location [SP-8]
>  fi#1: size=4, align=4, at location [SP-12]
>  fi#2: size=4, align=4, at location [SP-4]
> Function Live Outs: %V0
> 
> BB#0: derived from LLVM BB %entry
>    %V0<def> = LiRxImmX16 <es:_gp_disp>[TF=5]
>    SaveRaF16 32
>    %V1<def> = AddiuRxPcImmX16 <es:_gp_disp>[TF=6]
>    %V0<def> = SllX16 %V0<kill>, 16
>    %S0<def> = AdduRxRyRz16 %V1<kill>, %V0<kill>
>    %V0<def> = LiRxImmX16 0
>    SwRxRyOffMemX16 %V0, %SP, 24; mem:ST4[%retval]
>    SwRxRyOffMemX16 %V0<kill>, %SP, 20; mem:ST4[%i]
>    PHI <BB#1>
>    Successors according to CFG: BB#1
> 
> BB#2: derived from LLVM BB %for.body
>    Live Ins: %S0
>    Predecessors according to CFG: BB#1
>    %A0<def> = LwRxRyOffMemX16 %S0, <ga:@.str>[TF=2]; mem:LD4[<unknown>]
>    %V0<def> = LwRxRyOffMemX16 %S0, <ga:@printf>[TF=3]; mem:LD4[GOT]
>    %A1<def> = LwRxRyOffMemX16 %SP, 20; mem:LD4[%i]
>    %T9<def> = Move32R16 %V0
>    %A0<def,tied> = AddiuRxRxImmX16 %A0<tied>, <ga:@.str>[TF=6]
>    %GP<def> = Move32R16 %S0
>    JumpLinkReg16 %V0<kill>, <regmask>, %A0<imp-use,kill>, %A1<imp-use,kill>, %GP<imp-use,kill>, %T9<imp-use,kill>, %SP<imp-def>, %V0<imp-def,dead>
>    %V0<def> = LwRxRyOffMemX16 %SP, 20; mem:LD4[%i]
>    %V0<def,tied> = AddiuRxRxImmX16 %V0<tied>, 1
>    SwRxRyOffMemX16 %V0<kill>, %SP, 20; mem:ST4[%i]
>    BimmX16 <BB#1>
>    Successors according to CFG: BB#1
> 
> BB#1: derived from LLVM BB %for.cond
>    Live Ins: %S0
>    Predecessors according to CFG: BB#0 BB#2
>    %V0<def> = LwRxRyOffMemX16 %SP, 20; mem:LD4[%i]
>    %V1<def> = LiRxImmX16 9
>    BtnezT8SltX16 %V1<kill>, %V0<kill>, <BB#3>
>    BimmX16 <BB#2>
>    Successors according to CFG: BB#2(124) BB#3(4)
> 
> BB#3: derived from LLVM BB %for.end
>    Predecessors according to CFG: BB#1
>    %V0<def> = LwRxRyOffMemX16 %SP, 24; mem:LD4[%retval]
>    %S0<def> = LwRxSpImmX16 %SP, 28; mem:LD4[FixedStack2]
>    RestoreRaF16 32
>    JrRa16
> 
> # End machine code for function main.
> 
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