[LLVMdev] % in tablegen

[Khaled Mohammed]

Hi,

I am facing an issue with tablegen.

tablegen complains about not finding a register when % is used in the
instruction string.
error: unable to find register for '' (which matches register prefix)

I have copied an example (not the original). Note that i added %prefix_
before $sp register. Tablegen seems to interpret % as placeholder for
inserting register. Is there any way to make tablgen ignore the %? I have
tried '\' character, and two "%%". None worked.

// ADD <Rd>, sp, #<imm8>
// This is rematerializable, which is particularly useful for taking the
// address of locals.
let isReMaterializable = 1 in
def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs),
IIC_iALUi,
                   "add\t$dst, %prefix_$sp, $rhs", []>,
               T1Encoding<{1,0,1,0,1,?}> {
  // A6.2 & A8.6.8
  bits<3> dst;
  bits<8> rhs;
  let Inst{10-8} = dst;
  let Inst{7-0}  = rhs;
}


- Khaled
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