[LLVMdev] More Back-End Porting Troubles

[Fabian Scheler]

>> By using dump(CurDAG) I was finally able to find out the problematic
>> instruction. It was defined in TriCoreInstrInfo.td but did not have an
>> associated pattern (the pattern is empty '[]'). Furthermore, this
>> instruction was not used anywhere else in the TriCore back-end, so I
>> commented it out. This resulted in the same assertion being triggered
>> and again no pattern was associated with the problematic instruction.
>> After commenting out enough of these instructions the assertion was not
>> triggered any more, this is the current state.
>>
>> Is '[]' supposed to be a catch-all-pattern or a pattern that never
>> matches? Is this a problem that results from the back-end implementation
>> or is it a general problem (there are more back-ends having '[]'-
>> patterns).

> [Villmow, Micah] This just means that there is no pattern so the only way to generate this instruction is by manually generating it. We use this quite extensively in the AMDIL backend for memory operations and flow control. We generate pseudo-instructions that are selected at ISel time and then run custom passes that transform them into the real HW instructions. Since they aren't selected at ISel time, they have no pattern.

OK, so these patterns work as I expected :-) The astonishing thing
here is: I don't find a single place where such an SDNode is created
manually. And after commenting out these instructions from the
tablegen file everything seems to be fine, but if those
instruction-nodes were created manually, I should not be able to
compile the back-end, right?

Ciao, Fabian