[LLVMdev] [RFC] Bundling support in the PostRA Scheduler

[Pekka Jääskeläinen]

On 08/13/2012 06:16 PM, Sergei Larin wrote:
>> Another solution (which we use in TCE) is to use register renaming.
>
>    You do it in LLVM? Do you plan to upstream it?

Not in LLVM but with a custom scheduler framework.

Our target is quite unique (see the blog post for an example)
therefore it's not completely clear (yet) how to map it to the LLVM
codegen/machineinstructions the best way while still exploiting the
unique optimizations of TTA. I've been following the activity on VLIW
support of LLVM in the hopes we can someday move more towards LLVM code
base.

I didn't know about the "post-RA sched. antidep breakers" in LLVM codegen
of which idea sound similar to what we do.

> Also, I do not know your target/goal, but do you look at global scheduling
> at all?

Only somewhat at this point (branch delay slot filling from the
target BB). Region scheduling and speculation is something that is
interesting but it hasn't been the "biggest itch" yet in our projects
therefore not implemented yet. I see efficient predication support as
highest priority (e.g. hyperblocks) for VLIWs.

BR,
-- 
--Pekka