[LLVMdev] TableGen related question for the Hexagon backend

[Jakob Stoklund Olesen]

On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote:
> 
> Currently, we rely on switch tables to transform between formats. However,
> we would like to have a different mechanism to represent these relationships
> instead of switch tables. I am thinking of modeling these relations in
> HexagonInstrInfo.td file and use TableGen to generate a table with the
> information.

That would be a good idea. X86 could also use some help with opcode mapping tables.

> Idea is to have a new class, say Relations, with some members
> of type 'Instruction' each representing a specific relation between itself
> and 'ThisInstr'.
> 
> For example:
> class Relations {
>                Instruction ThisInstr;
>                Instruction BaseForm;
>                Instruction TruePred;
>                Instruction FalsePred;
> }
> 
> def Rel_ADDrr : Relations<ADDrr, ADDrr, ADDrr_p, ADDrr_np>;
> def Rel_ADDrr_p: Relations<ADDrr_p, ADDrr, , >;
> def Rel_ADDrr_np : Relations<ADDrr_np,ADDrr, , >;

The problem is, this isn't really any better than having a large switch statement. You just moved the table into the .td file.

You should be taking advantage of the instruction multiclasses so you don't have to maintain a full table of opcodes.

/jakob