[LLVMdev] [PATCH][RFC] Add llvm.codegen Intrinsic To Support Embedded LLVM IR Code Generation

[Evan Cheng]

On Apr 29, 2012, at 6:37 AM, Tobias Grosser wrote:

> 
> OK, I get what you mean. The intrinsic is currently targeted at the 
> OpenCL/CUDA model. It is the most widely used. Stuff like cell sounds 
> interesting, but probably needs further thoughts. Even with OpenCL/CUDA,
> this intrinsic works currently only for PTX code generation, but I hope 
> we can gain support for other GPU devices later on.
> 
>>    I agree that future work can be useful here. However, before
>>    spending a large amount of time to engineer a complex solution, I
>>    propose to start with the proposed light-weight approach. It is
>>    sufficient for our needs and will allow us to get the experience and
>>    infrastructure that can help us to choose and implement a more
>>    complex later on.
>> 
>> 
>> I agree that this approach is the best way to get short-term results,
>> especially for the GSoC project.
> 
> OK, let's go ahead.
> 
> Yabin, can you update the patch with the following changes:
> 
> - Remove the Arch flag
> - Document that we require a triple
> - Add two new arguments that take a feature string and a mcpu
>   flag (can be set to "", which means we use the default)

Wait. I don't think there is enough justification for this to move forward. Apart from the technical issues that have already been raised. I can also see this introduces a safety issue since the embedded IR code is not checked / verified at compile time. Unless Chris says otherwise, I don't see this patch being accepted on trunk.

Evan

> 
> Cheers
> Tobi
> 
> 
> 
> 
> 
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