[LLVMdev] Not enough optimisations in the SelectionDAG phase?

[Fan Dawei]

For the following code fragment,

; <label>:27                                      ; preds = %27, %entry
  %28 = load volatile i32* inttoptr (i64 2149581832 to i32*), align 8
  %29 = icmp slt i32 %28, 0
  br i1 %29, label %27, label %loop.exit

loop.exit:                                  ; preds = %27

llc will generate following MIPS code,

$BB0_1:
  lui $3, 32800
  ori $3, $3, 1032
  lw  $3, 0($3)
  bltz  $3, $BB0_1
  nop
# BB#2:


The two operation lui and ori which are used to calculate memory address
actually are loop invariants. They supposed to be moved out of the loop.  I
thought it might be a limitation of the MIPS backend.  Then I tried the ARM
backend,

 .LBB1_1:
  ldr r2, .LCPI1_2
  ldr r2, [r2]
  cmp r2, #0
  blt .LBB1_1
@ BB#2:

The first ldr instruction is to load the address from constant pool. It
also should be outside the loop.

I'm not sure if this is because of the optimisations are not enough in the
common SelectionDAG optimisation phase, or  should this kind of
optimisation be implemented by the SelectionDAG instruction lowering phase
for each target?
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