[LLVMdev] CriticalAntiDepBreaker rewrites a register operand of a call instruction

[Akira Hatanaka]

Hi Anton,

Thanks for the suggestions.

I compiled the .ll file with llc with command line options
-verify-dom-info, -verify-regalloc and -verify-loop-info.
I didn't see any diagnostic messages.

When I add -verify-machineinstrs, it complains that there are instructions
after terminator instructions.
It seems that these error messages are printed because the verifier does
not understand that mips has delay slots, not because it has detected any
true violations.

$ llc macroblock.llvm.mips64el.ll -mcpu=mips64r2 -O3 -o macroblock.s
-mattr=n64 -verify-machineinstrs

# After PreEmit passes
# Machine code for function start_macroblock: Post SSA

BB#0: derived from LLVM BB %entry
    Live Ins: %A0_64 %T9_64 %RA_64 %S3_64 %S2_64 %S1_64 %S0_64
    BEQ %A0<kill>, %ZERO, <BB#2>
    NOP
    Successors according to CFG: BB#2 BB#1

# End machine code for function start_macroblock.

*** Bad machine code: MBB exits via unconditional fall-through but doesn't
have exactly one CFG successor! ***
- function:    start_macroblock
- basic block: entry 0x3ce4700 (BB#0)

*** Bad machine code: Non-terminator instruction after the first terminator
***
- function:    start_macroblock
- basic block: entry 0x3ce4700 (BB#0)
- instruction: NOP
First terminator was:    BEQ %A0<kill>, %ZERO, <BB#2>

On Fri, Apr 20, 2012 at 9:50 PM, Anton Korobeynikov <anton at korobeynikov.info
> wrote:

> Hi Akira,
>
> > I am running into a problem when I turn on post-RA scheduler with mode
> > "ANTIDEP_CRITICAL" for mips.
> > I'd appreciate if someone could explain what is going wrong here.
> All these passes are pretty sensitive to correct register liveness
> information. As a first step I'd check whether machine verifier
> reports no errors here.
>
> --
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University
>
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