[LLVMdev] Registers and isel type inference

[Jakob Stoklund Olesen]

So I tried adding a new register class to the x86 target:

  def WIDE32 : RegisterClass<"X86", [i32, f32], 32, (add GR32, FR32)>;

I thought this would be a harmless thing to do since the new register class is not being referenced anywhere.  I was wrong, it caused all kinds of assertion failures from tablegen's isel pattern generator.

It appears that tablegen is inferring the 'type' of an individual register by enumerating all the register classes it appears in.  Some things, like using implicit defs in SDNodes, only works for registers with a unique type.  My WIDE32 class caused GR32 registers to no longer have a unique type, breaking the world.

This seems too fragile to me.  Besides my current experiments with wide register classes, Blackfin's general purpose registers can hold both i32 and v2i16 types.  Does that mean Blackfin instructions can't use GPR implicit defs as SDNode results?

I would like to fix this, but I am not sure how.  I could:

- Disable type inference for individual registers entirely, or

- Add a ValueType field to the Register tablegen class, so types are not inferred by enumerating register classes.

Any suggestions?

/jakob