[LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits

[Duncan Sands]

This patch synthesizes haddps/haddpd/hsubps/hsubpd instructions from floating
point additions and subtractions of appropriate vector shuffles.  To do this I
introduced new x86 FHADD and FHSUB opcodes.  These need to be wired up somehow
in the .td file to the appropriate instructions.  Since I have no idea how
tablegen works I just hacked it in horribly.  It works, but breaks support for
the hadd etc intrinsics (if you take a look at how I did it you will see why!).
I'm sending the patch for comments, and in the hope that someone will explain
how I should be doing the tablegen bits.

Ciao, Duncan.
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