[LLVMdev] fastcc lowering

[Garrison Venn]

Beyond looking at the result of code gen, or tracing through LLVM source. Is there a way
to determine whether or not an applied fastcc function attribute (applied also at call site), 
will manifest itself as a register only (non-stack) function call. Even though I believe this 
is a code gen issue, is there an analysis pass which would indicate this direction will be 
taken? Baring that can I turn on an existing define, or use some other such mechanism 
for an LLVM debug, or other build that will give me this info? 

In general, I'm under the current impression that when operating in the IR paradigm, one cannot 
ask, or contemplate questions concerning code gen given that it is mostly platform independent, 
and that future applied optimization passes can radically transform the IR. Questions like: will the 
use of a phi loop over a switch instruction vs a phi loop over a constant array go against the 
grain of branch prediction as the block target will most likely be different for each iteration in the
switch case; or will designation of fastcc really result in a register based call and return etc. Is this 
a correct understanding of the IR view--that it is not the province for such questions?

Thanks in advance

Garrison