[LLVMdev] Some questions on SelectionDAG

[Zakk]

Hi, all



I am studying the ARM backend on SelectionDAG, I have some following
questions:



1. Each operator of SDNode in SelectionDAG is required to be defined by
SDNode<ISD::XXX,XXX,XXX> in .td file, right?

But several operators are not defined in .td file, why? (e.g., ISD::BR_CC,
ISD::CopyToReg, ISD::AssertSext)



2. The MVT::glue value is used to ensure two nodes are scheduled together
and in order.

In the other word, we can’t insert any instruction of them in the
scheduling, is it correct?



3. In the ARMISelLowering constructor, it sets the callback function with

setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);

My question is ARM don’t support MVT::i1 registerclass, why should it
determine this operation with MVT::i1 value?



Can anyone tell me?

Thank you very much.




Best regards,

Zakk
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